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THC63LVD824 _Rev2.0
THC63LVD824
Single(135MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA
General Description
The THC63LVD824 receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions. The THC63LVD824 converts the LVDS data streams back into 48bits of CMOS/TTL data with falling edge or rising edge clock for convenient with a variety of LCD panel controllers. In Single Link, data transmit clock frequency of 135MHz, 48bits of RGB data are transmitted at an effective rate of 945Mbps per LVDS channel. Using a 135MHz clock, the data throughput is 472Mbytes per second. In Dual Link, data transmit clock frequency of 85MHz, 48bits of RGB data are transmitted at an effective rate of 595Mbps per LVDS channel. Using a 85MHz clock, the data throughput is 595Mbytes per second.
Features
* Wide dot clock range: 25-170MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
* PLL requires No external components * Supports Single Link up to 135MHz dot clock for
SXGA+
* Supports Dual Link up to 170MHz dot clock for * * * * * * *
UXGA 50% output clock duty cycle TTL clock edge programmable TTL output driverbility selectable for lower EMI Power down mode Low power single 3.3V CMOS design 100pin TQFP THC63LVDF84B compatible
Block Diagram
LVDS INPUT SERIAL TO PARALLEL RA1 +/RB1 +/1st Link RC1 +/RD1 +/RCLK1 +/(25 to 135MHz) 8 8 28 8 CMOS/TTL OUTPUT RED1 GREEN1 BLUE1 1st DATA
HSYNC VSYNC DEMUX
PLL
DE
SERIAL TO PARALLEL
RA2 +/RB2 +/2nd Link RC2 +/RD2 +/RCLK2 +/(25 to 85MHz)
RECEIVER CLOCK OUT (25 to 85MHz) 8 RED2 GREEN2 BLUE2 2nd DATA
28
8 8
PLL
R/F /PDWN
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD824 _Rev2.0
Pin Out
75 LVDS GND RA1RA1+ RB1RB1+ LVDS VCC RC1RC1+ RCLK1RCLK1+ RD1RD1+ LVDS GND RA2RA2+ RB2RB2+ LVDS VCC RC2RC2+ RCLK2RCLK2+ RD2RD2+ LVDS GND 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSYNC HSYNC B17 B16 GND VCC B15 B14 B13 B12 B11 B10 G17 G16 G15 G14 G13 GND VCC G12 G11 G10 R17 R16
DE
R15 GND VCC R14 R13 R12 R11 R10 GND VCC CLKOUT B27 B26 B25 B24 B23 GND VCC B22 B21 B20 G27 GND VCC G26
1 PLL GND
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
PLL VCC GND /PDWN MODE0 MODE1 GND R/F DRVSEL R20 R21 R22 R23 R24 VCC GND R25 R26 R27 G20 G21 G22 G23 G24 G25 2 THine Electronics, Inc.
THC63LVD824 _Rev2.0
Pin Description
Pin Name RA1+, RA1RB1+, RB1RC1+, RC1RD1+, RD1RCLK1+, RCLK1RA2+, RA2RB2+, RB2RC2+, RC2RD2+, RD2RCLK2+, RCLK2R17 ~ R10 G17 ~ G10 B17 ~ B10 R27 ~ R20 G27 ~ G20 B27 ~ B20 DE VSYNC HSYNC CLKOUT DRVSEL R/F Pin # 78, 77 80, 79 83, 82 87, 86 85, 84 90, 89 92, 91 95, 94 99, 98 97, 96 52, 51, 50, 47, 46, 45, 44, 43 62, 61, 60, 59, 58, 55, 54, 53 72, 71, 68, 67, 66, 65, 64, 63 19, 18, 17, 14, 13, 12, 11, 10 29, 26, 25, 24, 23, 22, 21, 20 39, 38, 37, 36, 35, 32, 31, 30 75 74 73 40 9 8 Type LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN IN Data Enable Output. Vsync Output. Hsync Output. Clock Output. Output Driverbility Select. H: High power, L: Low power. Output Clock Triggering Edge Select. H: Rising edge, L: Falling edge. Pixel Data Mode. MODE1, MODE0 6, 5 IN
MODE1 L L MODE0 L H Mode Dual Link Single Link
Description
The 1st Link. The 1st pixel input data when Dual Link.
LVDS Clock Input for 1st Link.
The 2nd Link. These pins are disabled when Single Link.
LVDS Clock Input for 2nd Link.
The 1st Pixel Data Outputs.
The 2nd Pixel Data Outputs.
/PDWN VCC GND LVDS VCC LVDS GND
4 15, 27, 33, 41, 48, 56, 69 3, 7, 16, 28, 34, 42, 49, 57, 70 81,93 76, 88, 100
IN Power Ground Power Ground
H: Normal operation, L: Power down (all outputs are pulled to ground) Power Supply Pins for TTL outputs and digital circuitry. Ground Pins for TTL outputs and digital circuitry. Power Supply Pins for LVDS inputs. Ground Pins for LVDS inputs.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD824 _Rev2.0
Pin Name PLL VCC PLL GND
Pin # 2 1
Type Power Ground
Description Power Supply Pin for PLL circuitry. Ground Pin for PLL circuitry.
Absolute Maximum Ratings 1
Supply Voltage (VCC) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage Output Current Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10sec) Maximum Power Dissipation @+25 C -0.3V ~ +4.0V -0.3V ~ (VCC + 0.3V) -0.3V ~ (VCC + 0.3V) -0.3V ~ (VCC + 0.3V) -30mA ~ 30mA +125 C -55 C ~ +125 C +230 C 1.0W
Electrical Characteristics CMOS/TTL DC Specifications
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol VIH VIL VOH VOL IINC Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Current IOH= -2mA, -4mA (data) IOH= -4mA, -8mA (clock) IOL= 2mA, 4mA (data) IOL= 4mA, 8mA (clock)
0V VIN V CC
Conditions
Min. 2.0 GND 2.4
Typ.
Max. VCC 0.8
Units V V V
0.4 10
V A
LVDS Receiver DC Specifications
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol VTH VTL IINL Parameter Differential Input High Threshold Differential Input Low Threshold Input Current Conditions VOC= 1.2V VOC= 1.2V VIN= 2.4V / 0V VCC= 3.6V -100 20 Min. Typ. Max. 100 Units mV mV A
1. "Absolute Maximum Ratings" are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD824 _Rev2.0
Supply Current
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol Parameter Condition(*) VESA SXGA (60Hz), fCLKOUT = 54MHz VESA UXGA (60Hz), fCLKOUT = 81MHz VESA SXGA (60Hz), fCLKOUT = 54MHz VESA UXGA (60Hz), fCLKOUT = 81MHz /PDWN = L MODE<1:0>=LH CL=8pF, Vcc=3.3V MODE<1:0>=LL CL=8pF, Vcc=3.3V MODE<1:0>=LH CL=8pF, Vcc=3.3V MODE<1:0>=LL CL=8pF, Vcc=3.3V 148 173 mA A 87 99 mA 85 97 mA 57 66 mA Typ. Max. Units
Receiver Supply IRCCG Current (256 Gray Scale Pattern)
Receiver Supply IRCCW Current (Double Checker Pattern)
IRCCS
Receiver Power Down Supply Current
10
(*) VESA is a trademark of the Video Electronics Standards Association.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD824 _Rev2.0
256 Gray Scale Pattern CLKOUT Rx0/Gx0/Bx0 Rx1/Gx1/Bx1 Rx2/Gx2/Bx2 Rx3/Gx3/Bx3 Rx4/Gx4/Bx4 Rx5/Gx5/Bx5 Rx6/Gx6/Bx6 Rx7/Gx7/Bx7 x=1,2 DE Double Checker Pattern CLKOUT R1n/G1n/B1n R2n/G2n/B2n n=0~7 DE
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD824 _Rev2.0
Switching Characteristics
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol tRCP tRCH tRCL tRS tRH tTLH tTHL tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2 tRPLL tRCIP tCK12 Parameter CLKOUT Period Dual-in / Dual-out Single-in / Dual-out Min. 11.76 14.8 Typ. tRCIP 2tRCIP
t RCP ---------2 t RCP ---------2
Max. 40.0 80.0
Units ns ns ns ns ns ns
CLKOUT High Time CKLOUT Low Time TTL Data Setup to CLKOUT TTL Data Hold from CKLOUT TTL Low to High Transition Time TTL High to Low Transition Time Input Data Position0 (tRCIP = 7.4ns) Input Data Position1 (tRCIP = 7.4ns) Input Data Position2 (tRCIP = 7.4ns) Input Data Position3 (tRCIP = 7.4ns) Input Data Position4 (tRCIP = 7.4ns) Input Data Position5 (tRCIP = 7.4ns) Input Data Position6 (tRCIP = 7.4ns) Phase Lock Loop Set CLKIN Period Skew Time between RCLK1 and RCLK2 7.4 -0.25
t RCIP ------------ - 0.25 7 t RCIP 2 ------------ - 0.25 7 t RCIP 3 ------------ - 0.25 7 t RCIP 4 ------------ - 0.25 7 t RCIP 5 ------------ - 0.25 7 t RCIP 6 ------------ - 0.25 7
0.3tRCP 0.3tRCP 3.0 3.0 0.0
tRCIP -----------7 tRCIP 2 -----------7 tRCIP 3 -----------7 tRCIP 4 -----------7 tRCIP 5 -----------7 tRCIP 6 -----------7
5.0 5.0 +0.25
t RCIP ------------ + 0.25 7 t RCIP 2 ------------ + 0.25 7 t RCIP 3 ------------ + 0.25 7 t RCIP 4 ------------ + 0.25 7 t RCIP 5 ------------ + 0.25 7 t RCIP 6 ------------ + 0.25 7
ns ns ns ns ns ns ns ns ns ms ns ns
10.0 40.0
0.3t RCIP
AC Timing Diagrams TTL Outputs
TTL Output 8pF 20% TTL Output Load tTLH tTHL 20% 80% 80%
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD824 _Rev2.0
AC Timing Diagrams TTL Outputs
tRCH 2.0V 2.0V 2.0V
tRCL R/F = L 0.8V 0.8V R/F = H
CLKOUT
tRCP tRS
tRH
Rxn Gxn Bxn x = 1,2 n = 0~7
2.0V 2.0V 0.8V 0.8V
Phase Lock Loop Set Time
3.0V
VCC
RCLKx+/2.0V
/PDWN
tRPLL 2.0V
CLKOUT
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD824 _Rev2.0
Pixel Map Table for Single/Dual Link
1st Pixel Data 824 TTL Output Pin R10 R11 R12 R13 R14 R15 R16 R17 G10 G11 G12 G13 G14 G15 G16 G17 B10 B11 B12 B13 B14 B15 B16 B17 MSB MSB LSB MSB LSB TFT Panel Data LSB 24Bit R10 R11 R12 R13 R14 R15 R16 R17 G10 G11 G12 G13 G14 G15 G16 G17 B10 B11 B12 B13 B14 B15 B16 B17 18Bit R10 R11 R12 R13 R14 R15 G10 G11 G12 G13 G14 G15 B10 B11 B12 B13 B14 B15
2nd Pixel Data 824 TTL Output Pin R20 R21 R22 R23 R24 R25 R26 R27 G20 G21 G22 G23 G24 G25 G26 G27 B20 B21 B22 B23 B24 B25 B26 B27 MSB MSB LSB MSB LSB TFT Panel Data LSB 24Bit R20 R21 R22 R23 R24 R25 R26 R27 G20 G21 G22 G23 G24 G25 G26 G27 B20 B21 B22 B23 B24 B25 B26 B27 18Bit R20 R21 R22 R23 R24 R25 G20 G21 G22 G23 G24 G25 B20 B21 B22 B23 B24 B25
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD824 _Rev2.0
824 TTL Data Output Timing for Single/Dual Link Example : SXGA+(1400 x 1050)
HSYNC DE CLKOUT R1x/G1x/B1x R2x/G2x/B2x n = 0~7 #1 #2 #3 #4 #5 #6 #7 #8 1395 #1397 #1399 1396 #1398 #1400
#1
#2
#1399 #1400
TFT Panel (1400 x 1050)
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD824 _Rev2.0
AC Timing Diagrams LVDS Inputs
tRIP2 tRIP3 tRIP4 tRIP5 tRIP6 tRIP0 tRIP1
Ryx+/-
Ryx6
Ryx5
Ryx4
Ryx3
Ryx2
Ryx1
Ryx0
Ryx6
Ryx5
Ryx4
Ryx3
Ryx2
Ryx1
RCLKx+
Vdiff = 0V
Vdiff = 0V
x = 1,2 y = A,B,C,D
tRCIP
RCLK1+
Vdiff = 0V
tCK12
RCLK2+
Vdiff = 0V
Note: Vdiff = (Ryx+) - (Ryx-), (RCLKx+) - (RCLKx-)
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD824 _Rev2.0
LVDS Data Inputs Timing Diagrams in Single Link
Previous Cycle (2nd pixel data)
Current Cycle (1st pixel data)
RCLK1+
RA1+/-
R26'
R25'
R24'
R23'
R22'
G12
R17
R16
R15
R14
R13
R12
G22''
RB1+/-
G27'
G26'
G25'
G24'
G23'
B13
B12
G17
G16
G15
G14
G13
B23''
RC1+/-
HSYNC'
B27'
B26'
B25'
B24'
DE
VSYNC HSYNC
B17
B16
B15
B14
DE''
RD1+/-
B20'
G21'
G20'
R21'
R20'
x
B11
B10
G11
G10
R11
R10
x''
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD824 _Rev2.0
LVDS Data Inputs Timing Diagrams in Dual Link
Previous Cycle
Current Cycle
RCLK1+
RA1+/-
R16'
R15'
R14'
R13'
R12'
G12
R17
R16
R15
R14
R13
R12
G12''
RB1+/-
G17'
G16'
G15'
G14'
G13'
B13
B12
G17
G16
G15
G14
G13
B13''
RC1+/-
HSYNC'
B17'
B16'
B15'
B14'
DE
VSYNC HSYNC
B17
B16
B15
B14
DE''
RD1+/-
B10'
G11'
G10'
R11'
R10'
x
B11
B10
G11
G10
R11
R10
x''
RCLK2+
RA2+/-
R26'
R25'
R24'
R23'
R22'
G22
R27
R26
R25
R24
R23
R22
G22''
RB2+/-
G27'
G26'
G25'
G24'
G23'
B23
B22
G27
G26
G25
G24
G23
B23''
RC2+/-
x'
B27'
B26'
B25'
B24'
x
x
x
B27
B26
B25
B24
x''
RD2+/-
B20'
G21'
G20'
R21'
R20'
x
B21
B20
G21
G20
R21
R20
x''
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD824 _Rev2.0
Package
INDEX PIN No.1
100
76
75
0.5TYP 14.0SQ TYP 0.22 25 51 26 50 1.00 TYP 1.2MAX
Copyright 2000-2003 THine Electronics, Inc. All rights reserved 14
16.0SQ TYP
UNITS:mm
THine Electronics, Inc.
THC63LVD824 _Rev2.0
Notes to Users:
1. The contents of this data sheet are subject to change without prior notice. 2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay sufficient attention when designing circuits. Even if there are incorrect descriptions, we are not responsible for any problem due to them. Please note that incorrect descriptions sometimes cannot be corrected immediately if found. 3. Our copyright and know-how are included in this data sheet. Duplication of the data sheet and disclosure to other persons are strictly prohibited without our permission. 4. We are not responsible for any problems of industrial proprietorship occurring during THC63LVD824 use, except for those directly related to THC63LVD824's structure, manufacture or functions. THC63LVD824 is designed on the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects people's lives, etc.). In addition, when using THC63LVD824 for traffic signals, safety devices and control/safety units in transportation equipment, etc., appropriate measures should be taken. 5. We are making the utmost effort to improve the quality and reliability of our products. However, there is a very slight possibility of failure in semiconductor devices. To avoid damage to social or official organizations, much care should be taken to provide sufficient redundancy and fail-safe design. 6. No radiation-hardened design is incorporated in THC63LVD824. 7. Judgment on whether THC63LVD824 comes under strategic products prescribed by the Foreign Exchange and Foreign Trade Control Law is the user's responsibility. 8. This technical document was provisionally created during development of THC63LVD824, so there is a possibility of differences between it and the product's final specifications. When designing circuits using THC63LVD824, be sure to refer to the final technical documents.
THine Electronics, Inc. Wakamatsu Bldg, 6F 3-3-6, Nihombashi-Honcho, Chuo-ku, Tokyo, 103-0023 Japan Tel: 81-3-3270-0666 Fax: 81-3-3270-0688
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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